Pritish M.

Pritish M. is an experienced IC Design Engineer currently working at Broadcom since April 2023. Previously, Pritish contributed to Amazon Web Services (AWS) from January 2020 to April 2023, focusing on microarchitecture and RTL design for stream processors and leading FPGA design efforts. Prior roles include membership on the technical staff at Fungible, Inc., where Pritish led the microarchitecture design of networking components and collaborated with physical design teams. At Broadcom from March 2015 to February 2017, Pritish was involved in the RTL design of traffic managers for network switches. Earlier experience includes work at Tabula and Algo-Logic Systems, where Pritish specialized in networking applications, FPGA development, and packet header lookup design. Pritish holds a Master’s degree in Electrical Engineering from the University of Southern California and a Bachelor’s degree in Electronics Engineering from Mumbai University.