Pushpaak Ramesh

Pushpaak Ramesh is an experienced R&D Senior Manager at Broadcom since February 2016, leading a high-performing ASIC design implementation team while overseeing physical design processes and engaging with external customers to enhance project schedules and outcomes. Previously, Pushpaak served as a Technical Lead ASIC Design Engineer, successfully managing a worldwide design team focused on developing 3nm, 5nm, 7nm, and 16nm ASICs tailored for Artificial Intelligence and networking applications, achieving the successful tape-out of more than 10 ASICs. Prior to Broadcom, Pushpaak worked as an ASIC Design Engineer at Avago Technologies from March 2013 to February 2016. Pushpaak holds a Master of Science in Electrical Engineering (VLSI) from Colorado State University and a Bachelor of Technology in Electronics and Communications Engineering from SRM IST Chennai.