Raju Patel

Raju Patel is a Principal ASIC Design Engineer at Broadcom, where they have worked since 2003, bringing over 31 years of extensive experience in the complete RTL to GDSII flow. Raju has specialized in areas such as timing closure, low-power design verification, and physical implementation, contributing significantly to the fields of STA, synthesis, and formal verification. Prior to Broadcom, Raju held roles as a Lead Engineer at Ciena and an ASIC Design Engineer at several other firms. Raju earned both a Master of Science and a Bachelor of Science in Electrical Engineering from San Jose State University.