Rohan Katiyar

Rohan Katiyar is a Senior Design Engineer at Broadcom, where they have been working since 2025. With over five years of experience in custom layout, memory layout, standard cell layout, and physical verification across various technologies, Rohan has developed expertise in tools such as Cadence Virtuoso and Mentor Graphics Calibre. Prior to their current role, Rohan held positions as a Senior Layout Engineer at Mirafra Technologies and as a Design Engineer at RealSilicon, contributing to significant projects including a SOC chip with a 10GHz processor. Rohan holds a Bachelor of Technology degree in Electrical, Electronics, and Communications Engineering from Bundelkhand University, where they studied from 2010 to 2014.