Sagar P

Sagar P is a Principal DFT Engineer at Broadcom with over 20 years of experience in Design-For-Test methodologies, specializing in DFT architecture, implementation, and verification across various complex semiconductor designs. They have held significant roles at companies such as Intel, AMD, and Synopsys, contributing to innovations in JTAG interfaces, test mode controllers, and analog DFT for custom SoC blocks. Previously, Sagar was a Distinguished DFT Lead Engineer at Semiconductor Services, where they enhanced DFT practices and methodologies. They possess extensive knowledge in tools and techniques relevant to ATPG, LBIST, boundary scan, and post-silicon debugging.