Sireesh Kumar

Sireesh Kumar is a Principal Engineer at Broadcom Inc., specializing in building Functional Verification environments using various methodologies and SystemVerilog-based directed test benches. They have extensive experience in the full flow of functional verification, from test plan development to coverage closure for tapeout, and have supported FPGA designers in post-silicon validation. Sireesh previously served as a Senior Design Verification Engineer at Avago Technologies, where they developed UVM-based verification environments for SerDes designs and MXS IP subsystems. They hold a B.Tech from Jawaharlal Nehru Technological University and a Master's in VLSI Design from C-DAC Noida.