Smit Bhavsar

Smit Bhavsar is an experienced Staff 1 IC Design Engineer at Broadcom since June 2012, specializing in block level design verification for memory controllers using VMM and System Verilog, along with updating and improving testbenches based on RTL changes. Prior to that, Smit worked as an intern in IC Design Verification, developing Perl scripts for register database maintenance and executing test cases related to SOC. Smit’s academic background includes a Master’s degree in Electrical and Electronics from San José State University and a Bachelor’s degree in Electronics and Telecommunication from JSPM's JSCOE. Additional experience includes roles as a Project Engineer at softcon system and a Trainee Engineer at Renu Electronics, focusing on client collaboration, CAD design, and embedded systems development.