Vinay Patil is a Senior Design Engineer specializing in Memory Design at Broadcom Inc., where they have been contributing since 2022. Prior to this role, they served as an R&D Engineer II at Synopsys Inc. from 2020 to 2022, focusing on memory circuit design. Vinay began their professional journey as a Teaching Assistant at the Indraprastha Institute of Information Technology, Delhi, in 2017, while also earning an M.Tech in VLSI and Embedded Systems from the same institution in 2019. They completed a Bachelor of Technology in Electronics and Telecommunication at Government Engineering College in Amravati between 2012 and 2016.
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