Yu HOU is a self-motivated and detail-oriented digital ASIC/SoC design engineer specializing in low power design and verification. With 17 years of hands-on experience, they have successfully taped out multiple high-volume wireless connectivity SoCs at Broadcom. Yu has engaged in SoC IP integration and RTL to GDSII flow development across various technology nodes ranging from 130nm to 7nm. Currently, they are pursuing both a Bachelor of Science and a Master of Science in Electrical and Electronics Engineering at Tsinghua University, along with a Master of Science in VLSI Design from the University of Southern California.
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