Bashar A.

Bashar A. is a Senior Principal Design Firmware Engineer at Cadence Design Systems since October 2020, with extensive experience in firmware and Linux development. Prior to this role, Bashar A. served as a Senior Member of Technical Staff Firmware Engineer at Microchip Technology Inc., where significant contributions included enhancing U-boot for hardware accelerated authentication and developing a clock driver for RISC-V RV64 SoC products. Bashar A. also held positions as a Principal Test Development Engineer at Microsemi, where the first secure manufacturing environment for FPGA SoC products was architected, and as a Staff Yield Enhancement Engineer and Yield Enhancement Engineering Intern at Actel (now Microsemi), focusing on yield enhancement and debugging for flash-based FPGA products. Educational qualifications include an M.S. in Computer Engineering from San José State University and a BASc in Engineering Science from the University of Toronto.