Abdullah Rabbani

Abdullah Rabbani is a VLSI Design Verification Engineer at Capgemini since April 2022, specializing in Verilog and Universal Verification Methodology (UVM) along with over nine additional skills. Prior to this role, Abdullah worked as a Freelance Software Developer from January 2020 to April 2022, focusing on HTML and Python, among other skills. Additionally, Abdullah gained experience as a Data Analyst at Refinitiv, an LSEG business, for a brief period in late 2019. Abdullah holds a Bachelor of Engineering degree in Electrical and Electronics Engineering from BNM Institute Of Technology, completed in May 2019.