Mohamed Y.

Mohamed Y. is a Senior Manager in ASIC Engineering at Ciena, bringing over eight years of experience in hardware and software system design and verification. With a strong foundation in hardware description languages such as Verilog, VHDL, and System Verilog, they also specialize in formal verification frameworks and object-oriented programming using Python and C++. Mohamed has held various academic positions, including Research Assistant at Concordia University and part-time Professor at the University of Ottawa, and has contributed significantly as a Senior ASIC Verification Engineer at Infinera. They earned both a Master's degree in Hardware Formal Verification and a PhD in Formal Analysis of Quantum Optics, achieving top honors in their studies.