Prit Patel

Prit Patel is an ASIC Engineer 2 at Ciena since June 2025, previously serving as an ASIC Physical Design Engineer at SignOff Semiconductors from January 2022 to February 2025, with expertise in various technology nodes including 4nm, 16nm, and 130nm. Prit's skill set encompasses static timing analysis (STA), full-chip timing, place and route (PnR), signoff checks, synthesis, floorplanning, and DRC & LVS. Prit gained experience as a Graduate Research Assistant at the University of Windsor from September 2019 to December 2020, focusing on FPGA applications in image processing and reconfigurable computing within VLSI and FPGA. As an Undergraduate Research Assistant at G.H. Patel College of Engineering and Technology, Prit contributed to the design of a wearable device for tracking human body parameters. Prit holds a Master of Applied Science in Electrical and Computer Engineering from the University of Windsor and a Bachelor of Engineering in Electronics and Communication from G.H. Patel College of Engineering & Technology.