Sasha Garg

Sasha Garg is an experienced engineer specializing in FPGA and ASIC design, currently working at Ciena since March 2020. Prior to this role, Sasha held positions at VVDN Technologies as a PhD Intern and at Mentor Graphics as a QVIP Engineer, focusing on verification IP development. Earlier experiences include serving as a Teaching Assistant at IIIT-Delhi, a Research Assistant and Research Scholar at Indraprastha Institute of Information Technology, and an intern at TCS Innovation Labs. Educational qualifications include a Master of Technology in Communication and Signal Processing from Indraprastha Institute of Information Technology, and a Bachelor of Technology in Electronics and Communication Engineering from ITM University. In addition, participation in a GIPEDI internship at the Indian Institute of Technology, Delhi, focused on Free Space Optical Communication enhances the academic profile.