Sreenath Nair is a Senior FPGA Engineer at Ciena since March 2022, bringing extensive experience in hardware design and development. Prior roles include FPGA/ASIC Design Engineer at Cisco from September 2018 to January 2022, and Senior Design Engineer at Cerium Systems from April 2017 to September 2018. Sreenath began a career as a Hardware Engineer at Agiliad from August 2014 to April 2017. Sreenath holds a PG-DVLSI in VLSI from ACTS-CDAC, Pune, obtained in 2014, and a Bachelor of Engineering in Electronics and Communications Engineering from B.H. Gardi College of Engineering and Technology, G.T.U, completed in 2013.
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