Srirup Bagchi is an experienced engineer with a background in electronics and telecommunication engineering. Srirup earned a Bachelor of Engineering degree from Jadavpur University in 2016 and is currently pursuing a Master of Applied Sciences in Electrical and Computer Engineering at the University of Toronto, expected to complete in 2025. Professional experience includes roles as a Design Engineer at Silicon & Beyond, followed by various positions at Synopsys Inc, culminating in a senior role as an AMS Circuit Design Engineer. Currently, Srirup serves as an Analog Engineer 3 at Ciena, with a research focus as a Graduate Student Researcher at the University of Toronto.
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