Swarda Shete is a Senior Engineer specializing in RTL Design at Qualcomm CWF, with a strong proficiency in RTL coding and validation using VHDL and Verilog. Swarda previously worked as a Design Engineer II at Cientra and as a Trainee Design Engineer at JDMTech Semiconductor Pvt. Ltd. Swarda holds a Bachelor of Engineering in Electronics and Communication Engineering from Rashtrasant Tukadoji Maharaj Nagpur University and a Diploma in Electronics and Communications Engineering from KDK Nagpur Polytechnic.
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