Soubickchane R.

Soubickchane R. has a strong background in electronics and FPGA design, with experience at CEA focusing on the study of electronic noise in ERAM MicroMegas detectors, alongside developing automated quality control tools for the Euclid space telescope project. Currently working as an FPGA Verification and Validation Engineer at CILAS, Soubickchane specializes in SystemVerilog testbenches for video processing systems, ensuring compliance with DO-254 standards. Past experience as an FPGA Design Engineer at THALES DMS FRANCE SAS involved benchmarking and designing FPGA solutions for data aggregation and communication. Soubickchane holds a Master 1 from Université Gustave Eiffel and is pursuing a Master 2 at Sorbonne Université, with earlier educational qualifications including a Licence and a scientific Baccalauréat.