Alessandro Cevrero is a principal engineer specializing in SerDes analog mixed-signal circuit design and silicon validation for advanced technologies, including 14nm FinFET and below. They held the position of research scientist at IBM from 2014 to 2018, focusing on high-speed circuit design and validation. Alessandro also served as a PhD student at École polytechnique fédérale de Lausanne, where they worked on high-speed I/O link circuit design and 3D integration technologies from 2008 to 2014. Currently, they are a principal engineer at Cisco, leading efforts in analog high-speed SerDes circuit design. Additionally, Alessandro has contributed to the field as an ASIC engineering technical leader, further advancing high-speed SerDes analog design.
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