Amer Badarnih is a seasoned engineering professional specializing in design verification, currently serving as a Sr. Design Verification Engineer at Cisco since January 2025. Prior experience includes roles as Senior Hardware Design Verification Engineer at Progineer Technologies from November 2021 to December 2024, and Design Verification Engineer at ASAL Technologies from December 2016 to November 2021, with a focus on formal and functional verification and Python scripting. Additionally, Amer contributed expertise in Verilog and System Verilog during a brief tenure at Veriest in early 2017. Amer Badarnih holds a Bachelor of Engineering degree in Computer Engineering from Arab American University, completed in 2016.
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