Davit Astvatsatryan is a Senior ASIC Physical Design Engineer at Cisco since 2025, bringing over 10 years of expertise in the semiconductor industry. Prior to their role at Cisco, Davit worked at Synopsys Inc. as a Senior Static Timing Analysis Engineer from 2021 to 2024 and held the position of SRAM Memory Compiler Engineer from 2015 to 2021. Davit completed a Bachelor's degree in Radiophysics at Yerevan State University in 2011 and obtained a Master's degree from the European Regional Academy in 2015.
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