Gian F.

Gian F. is an ASIC Design Engineer at Cisco Acacia, specializing in ASIC synthesis and integration. They previously worked at Intel Corporation as a Senior Software/CAD Engineer, where they drove RTL power reduction methodologies and developed workflows using Python, Perl, and TCL. Gian contributed to machine learning initiatives for CAD power tools, creating Supervised Machine Learning flows for SoC power optimization. Earlier in their career at Intel, they also served as a Component Design Engineer, developing electronic rule checking software and providing pre-silicon physical design support. They earned a degree from the Georgia Institute of Technology between 2017 and 2020.