Jitender Kaul is an ASIC Engineering Technical Leader at Cisco, where they have been since 2016. With over 20 years of experience in ASIC design verification, Jitender has previously held roles at Mirafra Technologies, Transwitch, Freescale Semiconductor, and Intel. Jitender completed a Master of Engineering in Microelectronics and a Bachelor of Engineering in Electrical and Electronics from Birla Institute of Technology and Science.
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