Khaled Kabil

Khaled Kabil is a Design Verification Engineer with extensive experience in ASIC and emulation verification. They have worked at several companies including Si-Vision, where they held positions as Senior Team Lead, Senior Staff Verification Engineer, and Staff Verification Engineer, focusing on subsystem IP testing. At Cisco, Khaled currently serves as a Leader in Hardware Engineering, applying expertise in System Verilog, UVM, VMM, SVA, and Verilog. They previously contributed to projects at IC-Pedia, Synopsys, and Mentor Graphics, developing verification environments and testing various memory protocols. Khaled earned a degree from Nile University in 2016.