Leo Z. is a Technical Lead at Cisco, specializing in FPGA/ASIC design verification with over 15 years of experience in network applications. Previously, Leo worked as a Senior Design Verification Engineer at ZTE, focusing on chip-set verification for DSLAM/Broadband Access and Gigabit ethernet switches. Leo holds a Bachelor's degree in Electrical Engineering from the University of Electronic Science and Technology of China, where they studied from 1995 to 1999. Their expertise includes SystemVerilog, UVM/VMM methodologies, and high-speed interface technologies.
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