Mital Patel

Mital Patel is currently a Technical Leader in ASIC Design Verification at Cisco, where they leverage their extensive expertise in ARM-based multi-processor and multi-core ASIC verification. With a strong background in design verification, Mital has previously held positions as a Sr. Design Verification Engineer at Cisco and as a Staff Engineer at both MediaTek and Broadcom. Mital began their career as an ASIC Design Verification Engineer at eInfochips, further developing their skills in RTL, simulation, and power-aware verification throughout their various roles. Mital is pursuing a B.E. in Electronics and Communication from North Gujarat University.