Prajwal K. is a Technical Lead ASIC Engineer at Cisco, specializing in mixed signal design and verification. With a solid foundation in RTL design and System Verilog based verification, Prajwal has extensive hands-on experience in high-speed silicon-photonic SERDES technologies. Prajwal's previous roles include research assistant at Utah State University and ASIC Engineer at Cisco, where they contributed to the design of over 100Gbps Ethernet SERDES chips. Prajwal holds a Master of Science in Electrical and Electronics Engineering from Utah State University and a Bachelor of Engineering from the University of Mumbai.
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