Vikas Khandelwal

Vikas Khandelwal is an experienced engineering professional specializing in hardware and ASIC verification, with a robust background in designing and implementing connectivity solutions. Currently serving as Director of Hardware Engineering at Cisco since July 2021, Vikas has played a pivotal role in establishing verification processes and leading teams in the successful delivery of advanced chips, including the industry's first PCIe Gen5 retimer. Prior to Cisco, Vikas held significant positions, including Head of ASIC Verification at Astera Labs, where Vikas contributed to innovative connectivity solutions for AI and machine learning applications, and Director of HW Engineering at Innovium Inc. Vikas's extensive experience spans multiple companies, including notable roles at SanDisk, HGST, and Cadence Design Systems, demonstrating a consistent focus on ASIC verification and hardware engineering. Vikas earned a Bachelor of Technology (B.Tech.) degree in Electrical Engineering from the Indian Institute of Technology, Kanpur.