Yejun Xie is a seasoned professional in ASIC engineering, holding the position of Manager, ASIC Engineering at Cisco since November 2006. Xie manages the Data Plane Chiplet Design & Verification Team, contributing to the development of Nexus 7K/ASR 9K Switching and Routing chips in China. Previously, Xie served as an ASIC Engineer/Team Lead, focusing on various high-speed switching chips, including the Nexus 3K and Nexus 7K. Earlier experience includes a role as an FPGA Engineer at Huawei-3Com from December 2004 to October 2006. Xie's academic background includes a Bachelor's degree in Precision Machinery and Precision Instrumentation from the University of Science and Technology of China, completed in 2004.
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