Chen Yang

Chen Yang, PhD has an extensive work experience in various roles and companies.

From September 2019 onwards, Chen Yang has been working at Citadel Securities as a Low Latency FPGA Engineer.

Prior to this, Chen Yang was affiliated with Boston University from September 2014 to August 2019. During this time, Chen Yang served as a Research Assistant and a Graduate Teaching Fellow.

In 2017, Chen Yang briefly worked at Argonne National Laboratory as a Research Aide, where they contributed to the development of a FPGA based TeraOps/s Reconfigurable Inference Processor (TRIP) for Machine Learning applications. Their work was published as a Poster at the International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

In 2016, Chen Yang had an internship as a Quality Engineer at The MathWorks. Here, they designed and implemented scripts and tools, and tested multiple features.

In 2014, Chen Yang worked as a Software Engineer intern at Cadence Design Systems, and in 2013, they served as a Hardware Engineer intern at Verigo.

Chen Yang, PhD has a solid education background in the fields of Communication Infrastructure and Application Acceleration on Multi-FPGA Platforms, Electrical and Computer Engineering, and Electrical Engineering. From 2014 to 2020, Chen Yang pursued a Doctor of Philosophy (Ph.D.) degree in Communication Infrastructure and Application Acceleration on Multi-FPGA Platforms at Boston University. Prior to that, from 2012 to 2014, Chen Yang completed a Master of Science degree in Electrical and Computer Engineering at the University of Florida. Chen Yang's education journey began at Wuhan University, where from 2008 to 2012, they earned a Bachelor of Engineering degree in Electrical Engineering.