Jerin Jacob

Jerin Jacob is a Principal Verification Engineer at Codasip, bringing over 15 years of expertise in FPGA IP and SOC verification. They have notable experience at companies such as Xilinx, where they contributed to the verification of HDMI IPs and the development of UVM-based testbenches, and at Imagination Technologies, focusing on RISC-V Processor verification. Jerin's background includes roles at ST-Ericsson and HCL Technologies, where they developed test plans and automated regression scripts. They hold a Bachelor of Technology in Electrical and Electronics Engineering from Maharshi Dayanand University and have completed various diplomas related to VLSI and financial analytics.