Xin Yang

Xin Yang is a Principal CPU Design Engineer at Codasip, specializing in RISC-V architecture since 2022. Previously, they served as a Senior Engineer in Network Security at Queen's University Belfast from 2011 to 2016, where they advanced memory architectures and supervised PhD candidates. Xin's earlier experience includes roles at CEVA, Inc. as a Principal Design Engineer and Design Team Lead, developing low-power DSP solutions, and at Leyard as a Project Engineer focusing on real-time DSP systems. They hold an MBA from Warwick Business School, completed in 2019, and had an industrial attachment at the Institute of Microelectronics in Singapore in 2001.