Zhenyu Pan

Zhenyu Pan has extensive work experience in CPU design and logic engineering. They are currently working as a Principal CPU Design Engineer at Codasip since September 2022. Prior to this, they held various roles at CEVA, Inc., including Design Team Lead from May 2021 to August 2022, Senior Logic Design Engineer from February 2018 to May 2021, and Logic Design Engineer from February 2017 to February 2018. Before joining CEVA, Inc., Zhenyu worked as a Design Engineer at Cirrus Logic from September 2014 to December 2016. They began their career as a Graduate Design Engineer at Wolfson Microelectronics in November 2012 and worked there until September 2014.

Zhenyu Pan obtained an MSc in Microelectronic System Design from the University of Southampton, starting in 2011 and completing in 2012. In addition to their degree, Zhenyu has obtained several certifications, including the edX Honor Code Certificate for Embedded Systems - Shape the World from edX in May 2016, the edX Honor Code Certificate for Computation Structures 2: Computer Architecture from edX in February 2016, The Hardware/Software Interface certification from Coursera in September 2014, and the edX Certificate for Introduction to Linux from edX in August 2014.