Jitendra G. has a strong background in engineering, holding a Bachelor of Technology in Electrical, Electronic and Communications Engineering from IMS Engineering College, completed in 2020. Jitendra G. began professional experience as a Subject Matter Expert at Chegg Inc. from April 2020 to January 2021, assisting students with academic support. Following this, Jitendra G. worked at the Centre for Development of Telematics (C-DOT) as a Senior FPGA/RTL Engineer from December 2024 to February 2025. Currently, Jitendra G. serves as a Senior FPGA/RTL Design Engineer at CP PLUS, starting in March 2025, and has held various engineering roles, including Senior FPGA Engineer at VVDN Technologies from September 2023 to November 2024 and earlier positions as an Intern and FPGA Engineer.
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