Syam K

Syam K has a diverse work experience in the field of electronics design and engineering. Syam is currently working as a Senior Electronics Design Engineer at Cradlewise Inc., where they contribute to the conceptualization of electronics hardware, designs and develops schematics, and oversees PCB PnR.

Prior to this, Syam worked at Qualcomm as a Lead Engineer from 2016 to 2020. In this role, they were involved in resource and power manager H/W block testing and its bring up in FPGA and silicon for Snapdragon 835 and 845 processors. Syam also played a role in DDR h/w validation and maintained software tools for core to DRAM path stress tests.

Syam's work experience also includes the position of System Engineer at NVIDIA from 2012 to 2016. During this time, they performed test case generation and silicon validation to check and verify clock gating and power gating features.

In addition, Syam worked as a Research Associate at IISc/Micro from 2008 to 2012. In this role, they worked on low-temperature CMOS characterization and measurement, co-developed BSIM models for 350nm CMOS devices, and had experience in designing analog front ends, interfacing with FPGA kits, and working with HDL.

Syam K completed their M.Tech degree at the Indian Institute of Science (IISc) from 2006 to 2010. Other than this, no specific information is provided regarding their education history.