Christine Bui

Christine Bui is an experienced Physical Design Engineer currently working at Cyient since September 2021, following a significant tenure with the same company as an ASIC Design Engineer from April 2011 to February 2020, interspersed with a break from work. Bui's expertise encompasses block level physical design processes utilizing 14nm, 32nm, and 45nm technologies, employing tools such as Cadence Innovus and Tempus for floorplanning, place and route, clock tree synthesis, and timing closure. Prior roles include contractor work at Zoran and a position as a Senior Design Engineer & Manager at Integrated Device Technology, where Bui contributed to product verification and design management. Early career experience at Integrated Circuit Systems involved physical design and training on various design tools and methodologies. Educational credentials include a VLSI Physical Design certification from UCSC extension and a Bachelor of Science in Electrical and Electronic Engineering from California State University-Sacramento.