Narendra Kumar R has extensive experience in analog and memory layout design, demonstrated through roles at prominent companies such as Tessolve, IBM, and Cyient Semiconductors. Narendra served as Sr. Design Lead at Tessolve and as a Design Lead at IBM, successfully executing memory layout projects with a focus on 7nm FinFET technology. Currently, as Technical Manager at Cyient Semiconductors, Narendra leads the analog and memory layout practice, emphasizing team development and client engagement. Previous positions include Design Engineer at STMicroelectronics, Sr. Design Engineer at Synopsys Inc, and Sr. Memory Layout Engineer at Arm, where responsibility for comprehensive layout execution and physical verification was established. Educational credentials include a B.Tech in Electronics and Instrumentation and a Master's in VLSI System Design.
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