Michel Vercier

Michel Vercier is an experienced FPGA Engineer at DRW since December 2015, with a robust background in digital design and verification across multiple organizations. Prior to this role, Michel served as a Design Verification Engineer for Intel Wireless Group from May 2014 to December 2015, focusing on the verification of LTE modem blocks. Michel's experience includes over a decade as a SOC Designer at Texas Instruments, contributing to various digital designs for power management and audio integrated circuits. Additional roles include Principal Engineer at Applied Micro, CoreWare Engineer at LSI Logic Corporation, Systems Engineer at In-Flight Phone Corporation, and Systems Engineer at Alcatel Telspace. Michel earned a B.S. in Electronics from École Nationale Supérieure de l'Électronique et de ses Applications from 1986 to 1989.