Entegro
Ramesh Jayasena is currently working at Entegro as an IP Design Engineer, focusing on quality control of FTTH network designs. Prior to this, Ramesh has held positions at various companies such as InSync Information Technologies, Level 3 Communications, and Dialog Axiata PLC. With a background in Mobile & Wireless Networks and Electronics & Telecommunication, Ramesh has extensive experience in network planning, implementation, maintenance, and project management in the telecommunications industry.
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