Deyang Jiang

Deyang Jiang is an ASIC Developer at Ericsson in Sweden, where they contributed to the design of in-house hardware accelerator IP and worked on UPF low power design in 2022. Previously, Deyang completed their Master’s thesis on machine learning-based instruction scheduling for a DSP architecture compiler. They also worked as a Research Assistant at the University of Wisconsin-Madison, focusing on a real-time Non-Line-of-Sight imaging system and improving the RSD algorithm. Deyang holds a Bachelor of Engineering in Electronic Information Engineering from ShanghaiTech University and a Master of Science in Embedded Systems from Kungliga Tekniska högskolan.