Gaurav Kakade has extensive experience in FPGA software development and verification, most recently serving as an FPGA IP Software Development Engineer at Intel Corporation from May 2021 to December 2023, contributing to centralized Tools Flows and Methodology for soft IP design and verification. Prior roles include serving as a System-on-Chip CAD Engineer, where Gaurav was involved in the development of methodologies and testing infrastructures for soft IP, and as a Pre-Silicon Verification Intern working on Intel's 3D NAND SSD technology. Gaurav also has a history of academic support roles at California State University-Sacramento. Currently, Gaurav is employed as an Engineer at Ericsson since July 2024.
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