Pavan Rao is an ASIC IP Architect at Ericsson, leading teams on various design verification projects since 2023. With over 12 years of experience in the semiconductor industry, Pavan previously served as a Logic Design Engineer at Intel Corporation from 2011 to 2018, where they contributed to front-end design and tool automation. Pavan's career also includes consultancy roles at Ericsson from 2018 to 2023 and training at Ansaldo STS, where they worked on safety systems for Southern Railways. Pavan holds a Master of Technology in Digital Communications from Vellore Institute of Technology, where they graduated with third rank and an impressive CGPA of 8.73.
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