Rashmi G.

Rashmi G. is an Electronics and Instrumentation graduate with a BE from Visvesvaraya Technological University, achieving a CGPA of 7.24. Currently a Senior Engineer at Eteros Technologies, Rashmi focuses on MIPI CSI/DSI interface verification at the SoC level and has a proven track record in the design and verification of digital blocks using SystemVerilog and UVM. Previously, Rashmi worked as an Engineer at MaxLinear and as a Design Verification Engineer at FrenusTech Pvt Ltd, where responsibilities included test plan creation and functional coverage analysis. Additionally, they completed a Graduate Engineering Trainee position at Bharat Electronics Limited. Passionate about digital electronics and eager to explore new technologies and opportunities, Rashmi actively connects within the VLSI and verification community.