Tirth Joshi

Tirth Joshi is a Senior Physical Design Engineer at Eteros Technologies, specializing in ASIC physical design. Tirth has experience in PnR, STA, EMIR, and PDV across various technology nodes, including 3nm, 5nm, and 7nm, utilizing tools such as DC Compiler, IC Compiler, ICC2, PrimeTime, Redhawk Fusion, and IC Validator. Prior to this role, Tirth worked as an ASIC Physical Design Engineer at eInfochips, where they were responsible for PnR and signoff activities and tackled dynamic and static IR issues. Tirth holds a BTech in Electronics and Communications Engineering from Dharmsinh Desai University and is pursuing an MTech in Microelectronics from the Birla Institute of Technology and Science, Pilani.