Stephen Ross

Stephen Ross is an accomplished FPGA Engineer at F5 since June 2019, progressing from FPGA Engineer I to III and serving as the Physical Design Team Lead. Responsibilities include managing weekly builds for timing closure and resource usage across multiple projects and executing RTL work for various FPGA devices from Altera and Xilinx. Proficient in VHDL, Verilog, SystemVerilog, and scripting languages such as TCL, Perl, and Python, Stephen demonstrates expertise in high-speed interface layout and RTL-wrapping. Prior experience includes an R&D Engineering Internship at Wagstaff, Inc., and service as a 25Q Multi-channel transmission-systems operator maintainer in the US Army, where leadership skills were cultivated. Educational background includes an Associate of Science degree in Electrical and Electronics Engineering from Spokane Falls Community College and further studies at Eastern Washington University.