Mengchen Yu

Mengchen Yu is a highly experienced professional in ASIC engineering, currently serving as Senior Director of ASIC Engineering at Fortinet since January 2015, focusing on ASIC/FPGA development for FortiGate products. Prior to Fortinet, Mengchen held the position of Senior Technical Leader at Cisco from November 2001 to January 2015, where responsibilities included multi-layer switching ASIC development for various Catalyst product lines. Earlier experience includes serving as a Senior ASIC Design Engineer at LSI Logic from April 1997 to November 2001, working on MIPS processor-based SOC development for the Sony PlayStation 2 and MIPS processor core development. Mengchen Yu holds a Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science in Electrical Engineering from Caltech.