Liji Joy

Liji Joy is a Junior FPGA Design Engineer at GMV since October 2022, focusing on the design of a single-chip navigation signal generator for satellite payloads using Zync RFSoC, as well as a prototype for the Lunar Communication and Navigation Services payload in S-band. Prior experience includes a position as an Advanced ASIC Verification Trainee at Maven Silicon from June 2022 to September 2022, where skills in Digital Electronics, Verilog, System Verilog, UVM, and RISC V Processor were developed, along with the design of a Router 1 x 3 using Verilog. Liji Joy also interned as a Design and Verification Intern at SION Semiconductors Private Limited from June 2021 to December 2021, acquiring knowledge in Verilog, System Verilog, UVM, advanced functional verification, and various protocols, culminating in the implementation of the UART protocol using Verilog. Educational qualifications include a Master of Technology in VLSI and Embedded System Engineering from S.C.M.S. School of Engineering Technology (2018 - 2020) and a Bachelor of Technology in Electronics and Communication Engineering from Sahrdaya College of Engineering & Technology (2014 - 2018).