Jared Cheng

Jared Cheng is an FPGA Design Engineer at RADAR since April 2025, with prior experience as a Full Cycle FPGA Engineer at Applied Signal Technology from August 2023 to April 2025 and an FPGA Intern at Raytheon Intelligence & Space in mid-2022. Throughout the career, contributions included IP Verification of Flash Memory Controllers, firmware support for advanced electronics systems, and extensive work in the development of mixed ionic electronic conductors and quantum CubeSat projects. Significant involvement in research at NASA Jet Propulsion Laboratory focused on optimizing data processing for the Mars 2020 Rover, alongside algorithm development for crystal diffraction patterns at the Materials Project at UC Berkeley. Jared Cheng holds a Bachelor of Applied Science in Materials Science and Engineering/Electrical Engineering and Computer Science from the University of California, Berkeley, obtained in 2023.