Amit Agrawal is an accomplished engineer with extensive experience in ASIC and logic design. Starting with a Technical Specialist role at Mindtree from February 2013 to December 2016, Amit focused on Bluetooth low energy IP design and development. Subsequently, a position as Senior Design Engineer at ON Semiconductor from December 2016 to April 2018 involved translating product requirements into RTL designs, specifically for Display Port 1. From April 2018 to June 2022, Amit served as a Senior Logic Design Engineer at Intel Corporation, where responsibilities included understanding low power design requirements and developing micro architectures for Integrated Sensor Hub IP. Currently, since July 2022, Amit is an ASIC RTL Design Engineer at Google. Amit holds a B.E. in Electronics & Communications from Charotar Institute of Technology and an M.Tech in VLSI Design from DA-IICT.
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