Anuj Srivastava

Anuj Srivastava is an experienced engineering professional with a strong background in ASIC design and development. From February 2015 to July 2016, Anuj served as an ASIC Design Engineer 2 and later as ASIC Design Engineer 3 at Juniper Networks. Prior to this role, Anuj worked at Tejas Networks from June 2011 to November 2014 as a Senior R&D Engineer. Anuj continued to advance in the field at Infinera, holding positions as Sr. ASIC Engineer and Staff ASIC Engineer from June 2019 to March 2021. Most recently, Anuj was a Senior Design Manager and RTL Design Manager at Google in May 2025. Anuj holds a Bachelor of Engineering in Electronics and Communication Engineering from Birla Institute of Technology, earned between 2007 and 2011, and completed SSC with a focus on PCM at City Montessori School from 2004 to 2006.